Electronic device, system-on-chip, and operating method thereof

ABSTRACT

An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2020-0110638 filed on Aug. 31, 2020, in the KoreanIntellectual Property Office, the disclosures of which are incorporatedby reference herein in their entireties.

BACKGROUND

The present inventive concept relates to a semiconductor memory, andmore particularly to, an electronic device, a system-on-chip, and anoperating method thereof.

A semiconductor memory is classified as a volatile memory, in whichstored data disappear when a power is turned off, such as a staticrandom access memory (SRAM) or a dynamic random access memory (DRAM), ora nonvolatile memory, in which stored data are retained even when apower is turned off, such as a flash memory, a phase-change RAM (PRAM),a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM(FRAM).

A cache memory may support an access speed higher than a main memory. Asa portion of data stored in the main memory is stored in the cachememory, a speed at which an access according to a request of a processoris made may be improved.

SUMMARY

Embodiments of the present disclosure provide an electronic devicecapable of minimizing power consumption with improved stability, asystem-on-chip, and an operating method thereof.

According to an embodiment of the present invention, an electronicdevice includes a cache memory including a memory space for storing afirst cache set including a plurality of sector data and a plurality ofdirty bits, each of the plurality of dirty bits representing whethercorresponding sector data of the plurality of sector data are modified,a memory controller, connected to a plurality of data lines and a datamask line, for receiving the plurality of sector data and the pluralityof dirty bits from the cache memory, setting a logic level of a datamask signal based on a logic level of each of the plurality of dirtybits, and outputting the plurality of sector data through the pluralityof data lines and the data mask signal through the data mask line, and amemory device, connected to the plurality of data lines and the datamask line, for receiving the plurality of sector data through theplurality of data lines, and receiving the data mask signal through thedata mask line.

According to an embodiment of the present invention, an operating methodof an electronic device which includes a cache memory including a memoryspace for storing a first cache set including a plurality of sector dataand a plurality of dirty bits, each of the plurality of dirty bitsrepresenting whether corresponding sector data of the plurality ofsector data stored in the cache memory are modified, a memory device,and a memory controller between the cache memory and the memory device,includes setting, by the memory controller, a logic level of the datamask signal based on a logic level of each of the plurality of dirtybits, issuing, by the memory controller, a first mask write (MWR)command to the memory device through command/address (CA) linesconnected thereto, and transmitting, by the memory controller, theplurality of sector data stored in the cache memory to the memory devicethrough a plurality of data lines connected thereto, and a data masksignal to the memory device through a data mask line connected thereto.

According to an embodiment of the present invention, a solid state drive(SSD) controller includes a cache memory including a memory storage forstoring a first cache set including first sector data and second sectordata, and a first dirty bit and a second dirty bit which are associatedwith the first sector data and the second sector data, respectively, anda buffer memory interface circuit for flushing, based on a logic levelof each of the first and second dirty bits, the first and second sectordata to an external memory device. The buffer memory interface circuitincludes a data mask control circuit which generates a data mask signaland outputs the data mask signal to the external memory device. The datamask control circuit sets a logic level of data mask signal based on thelogic level of each of the first dirty bit and the second dirty bit. Thelogic level of each of the first dirty bit and second dirty bitrepresents that a corresponding one of the first sector data and thesecond sector data is in one of a dirty state and a clean state.

According to an embodiment of the present invention, a memory deviceincludes a memory cell array including a plurality of memory cells, aninput/output circuit for receiving a plurality of sector data through aplurality of data lines, and a control logic circuit for receiving afirst mask write (MWR) command through command/address (CA) lines,receiving a data mask signal through a data mask line, and selectivelystoring the plurality of sector data in the memory cell array inresponse to the data mask signal. The data mask signal is generated froman external memory controller based on a plurality of dirty bitsassociated with the plurality of sector data, respectively.

According to an embodiment of the present invention, a cache memorysystem includes a cache memory including a memory space configured tostore a first cache set including a plurality of sector data and aplurality of dirty bits, each of the plurality of dirty bitsrepresenting whether corresponding sector data of the plurality ofsector data are modified, and a processor configured to perform a flushoperation on the first cache set so that the plurality of sector dataand the plurality of dirty bits are outputted to an external memorycontroller. The size of the first cache set is the same as the size of acache line which is a minimum access unit of data in the flushoperation.

According to an embodiment of the present invention, a memory controllerincludes a data mask control circuit. The data mask control circuitreceives a plurality of sector data and a plurality of dirty bits froman external cache memory, each of the plurality of dirty bitsrepresenting whether corresponding sector data of the plurality ofsector data are modified, generates a data mask signal based on theplurality of dirty bits, outputs the plurality of sector data to anexternal memory device through a plurality of data lines, and outputsthe data mask signal to the external memory device through a data maskline.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features of the present disclosure willbecome apparent by describing in detail embodiments thereof withreference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an electronic device according toan embodiment of the present disclosure.

FIG. 2 is a diagram for describing a cache structure of an electronicdevice of FIG. 1 .

FIGS. 3A to 3C are diagrams illustrating an operation of an electronicdevice.

FIG. 4 is a diagram for describing a cache set according to anembodiment of the present disclosure.

FIGS. 5A to 5C are diagrams illustrating an operation of an electronicdevice of FIG. 1 .

FIG. 6 is a flowchart illustrating an operation of a memory controllerof FIG. 1 .

FIG. 7 is a timing diagram illustrating operation S400 of FIG. 6 indetail.

FIG. 8 is a block diagram illustrating a memory device of FIG. 1 indetail.

FIGS. 9A and 9B are timing diagrams for describing an operation of amemory device of FIG. 1 .

FIGS. 10A to 10C are flowcharts illustrating operations of an electronicdevice of FIG. 1 .

FIG. 11 is a block diagram illustrating a storage device according to anembodiment of the present disclosure.

FIG. 12 is a block diagram illustrating a memory controller of FIG. 11 .

FIG. 13 is a block diagram illustrating an SSD system according to thepresent disclosure.

DETAILED DESCRIPTION

Below, embodiments of the present disclosure may be described in detailand clearly to such an extent that an ordinary one in the art easilyimplements the present disclosure.

FIG. 1 is a block diagram illustrating an electronic device according toan embodiment of the present disclosure. Referring to FIG. 1 , anelectronic device 1000 may include a system-on-chip (SoC) 1100 and amemory device 1200. In an embodiment, the electronic device 1000 may beone of various computing devices such as a desktop computer, a laptopcomputer, a workstation, a server, a smartphone, a tablet PC, a digitalcamera, and a black box.

The SoC 1100 may control overall operations of the electronic device1000. For example, the SoC 1100 may be an application processor (AP)which controls the overall operations of the electronic device 1000. TheSoC 1100 may run an operating system, a program, or an application thatis executable on the electronic device 1000.

The SoC 1100 may store data in the memory device 1200 or may read datastored in the memory device 1200. The SoC 1100 may include a processor1110, a cache memory device 1120 (i.e., a cache memory), and a memorycontroller 1130. The processor 1110 may perform various operations ofthe electronic device 1000 and may process data.

In response to a signal received from the processor 1110, the cachememory device 1120 may store data or may provide data stored therein tothe processor 1110. The cache memory device 1120 may support an accessspeed higher than the memory device 1200. For example, as a portion ofdata stored in the memory device 1200 is stored in the cache memorydevice 1120, a speed at which an access according to a request of theprocessor 1110 is made may be improved. In an embodiment, the cachememory device 1120 may be a static random access memory (SRAM) device,but the present disclosure is not limited thereto.

In an embodiment, the cache memory device 1120 may generate dirtyinformation DI. The cache memory device 1120 may transmit the dirtyinformation DI and data to the memory controller 1130. The dirtyinformation DI may indicate whether cache data loaded from the memorydevice 1200 are updated.

The memory controller 1130 may control the memory device 1200. Forexample, the memory controller 1130 may transmit an address ADDR, acommand CMD, a control signal CTRL, and a data mask signal DM to thememory device 1200 for the purpose of controlling the memory device 1200and may exchange data “DATA” with the memory device 1200 through a dataline DQ.

The memory device 1200 may operate under control of the memorycontroller 1130. For example, in response to signals received from thememory controller 1130, the memory device 1200 may store the data “DATA”or may provide the stored data “DATA” to the memory controller 1130. Inan embodiment, the memory device 1200 may be a dynamic random accessmemory (DRAM) device, but the present disclosure is not limited thereto.

In an embodiment, the memory controller 1130 and the memory device 1200may communicate with each other based on a given interface. The giveninterface may be a low-power double data rate (LPDDR), but the presentdisclosure is not limited thereto. For example, the given interface mayinclude at least one of various interfaces such as a DDR interface, auniversal serial bus (USB) interface, a multimedia card (MMC) interface,a peripheral component interconnection (PCI) interface, a PCI-express(PCIe) interface, an advanced technology attachment (ATA) interface, aserial-ATA (SATA) interface, a parallel-ATA (PATA) interface, a smallcomputer small interface (SCSI) interface, an enhanced small diskinterface (ESDI), an integrated drive electronics (IDE) interface, amobile industry processor interface (MIPI), and a nonvolatilememory-express (NVMe) interface.

In an embodiment, the memory controller 1130 may include a data maskcontrol circuit 1131. The data mask control circuit 1131 may receive thedirty information DI from the cache memory device 1120. The data maskcontrol circuit 1131 may output the data mask signal DM through a datamask line based on the received dirty information DI.

When the processor 1110 transmits a write request, write-requested datamay be temporarily stored in the cache memory device 1120 without beingimmediately transmitted to the memory device 1200. After data are storedin the cache memory device 1120 without writing the data to the memorydevice 1200, a write complete signal may be transmitted to the processor1110. This write operation is called a “write operation of a write-backmanner”. In contrast, when the processor 1110 transmits a write request,write-requested data may be stored in the cache memory device 1120 andmay be immediately transmitted to the memory device 1200. A writecomplete signal may be transmitted to the processor 1110 after the dataare stored in the memory device 1200. This write operation is called a“write operation of a write-through manner”.

When a write operation is performed in the write-back manner, a linefill operation (i.e., a cache fill operation) from the memory device1200 to the cache memory device 1120 may be performed, and data damagemay occur in the line fill operation. The line fill operation mayindicate the following operation: when a cache miss occurs in the cachememory device 1120, data corresponding to the cache miss are read fromthe memory device 1200, and the read data are stored in the cache memorydevice 1120. When there is an error on an interface (e.g., acommunication between the memory device 1200 and the cache memory device1120) or the cache memory device 1120 during the line fill operation,damaged data may be stored in the cache memory device 1120. Also, when aflush operation is performed on a cache line where the damaged data arestored, the damaged data may be stored in the memory device 1200.

In an embodiment, a cache line may be a minimum access unit of a read orwrite request that the processor 1110 transmits to the memory device1200. A size of each of cache lines may be, for example, 32 Bytes or 64Bytes, but the present disclosure is not limited thereto.

A conventional electronic device accesses a memory device in units ofcache line and manages dirty information in units of cache line. Theconventional electronic device may perform the line fill operation orthe flush operation on all the cache lines. In this case, when a portionof data included in a cache line is damaged, the damaged portion may bestored in the memory device.

In contrast, the electronic device 1000 according to an embodiment ofthe present disclosure may manage dirty information in units of sectorsmaller than a cache line. The electronic device 1000 may generate thedata mask signal DM based on dirty information managed in units ofsector and may perform a write operation on the memory device 1200 inunits of sector. Accordingly, a sector in the cache memory device 1120,which is not updated by the processor 1110, may not be stored in thememory device 1200 for data consistency between the cache memory device1120 and the memory device 1200. According to the above description,unnecessary data store operations may be minimized, and thus, an errorin the memory device 1200 may decrease. An operation of the electronicdevice 1000 according to the present disclosure will be described withreference to the following drawings.

FIG. 2 is a diagram for describing a cache structure of an electronicdevice of FIG. 1 . For convenience of description, components that areunnecessary to describe a cache structure of the cache memory device1120 will be omitted.

The cache memory device 1120 may include a plurality of cache sets CS1to CSn. A cache set CS may include a cache line and a cache entry. Thecache entry may include a valid bit “V”, a dirty bit “D”, and a tag TAG.In an embodiment, the format of the cache set CS includes a field forstoring data of the cache line, and a field for storing information ofthe cache entry.

The memory device 1200 may include a plurality of cache lines CL1 toCLm. The plurality of cache lines CL1 to CLm may indicate a storagespace corresponding to a unit of a data access according to a request ofthe processor 1110.

A portion of data stored in the memory device 1200 may be stored in thecache memory device 1120. In an embodiment, the first cache line CL1 maycorrespond to the first cache set CS1, the second cache line CL2 maycorrespond to the second cache set CS2, the third cache line CL3 maycorrespond to the third cache set CS3, and the m-th cache line CLm maycorrespond to the n-th cache set CSn.

A cache line may include first to fourth sectors S1 to S4. The first tofourth sectors S1 to S4 may have the same size. For example, when a sizeof a cache line is 64 Bytes, a size of a sector may be 16 Bytes.

The tag TAG may indicate address information about cache data stored ineach cache set. In an embodiment, the tag TAG may be informationindicating a cache line corresponding to cache data from among the cachelines CL1 to CLm of the memory device 1200. The tag TAG may be used todetermine whether data corresponding to an address received from theprocessor 1110 are present in the cache memory device 1120. The tag TAGmay be used to determine a cache hit or a cache miss. A cache hit mayindicate the case where data corresponding to an address received fromthe processor 1110 are present in the cache memory device 1120. A cachemiss may indicate the case where data corresponding to an addressreceived from the processor 1110 are absent from the cache memory device1120.

The dirty bit “D” may indicate whether after cache data are stored in acorresponding cache set, the cached data is updated. The dirty bit “D”may indicate whether cache data are identical to the corresponding datastored in the memory device 1200. In the case where no update is made,the dirty bit “D” may be maintained to indicate a clean state. In thecase where the update is made, the dirty bit “D” may be set to indicatea dirty state.

In an embodiment, the dirty bit “D” may have one of a first logicalvalue and a second logical value. The first logical value of the dirtybit “D” indicates that cached data associated with the dirty bit “D” andthe corresponding data stored in the memory device 1200 are identicalwith each other. The second logical the dirty bit “D” indicates thatcached data associated with the dirty bit “D” are updated, and thecached data and the corresponding data stored in the memory device 1200are different from each other.

The valid bit “V” may indicate whether valid data are loaded from thememory device 1200 to the corresponding cache set. The valid bit “V” mayrepresent one of a first logical value and a second logical value. Thesecond logical value of the valid bit “V” indicates an activated statein which valid data have been loaded from the memory device 1200 to thecorresponding cache set of the cache memory device 1120, and the firstlogical value of the valid bit “V” indicates an deactivated state inwhich no valid data have not been loaded from the memory device 1200 tothe corresponding cache set of the cache memory device 1120. In anembodiment, when the SoC 1100 is booted, the valid bit “V” may beinitialized to the first logical value, and upon uploading of valid datafrom the memory device 1200 to the cache memory device 1120, the validbit “V” changes to have the second logical value. In an embodiment wherethe processor 1110 includes multi-processor cores, the valid bit “V” maybe reset to the first logical value while in use.

Each of the plurality of cache lines CL1 to CLm may be selected orrecognized by an address provided from the processor 1110. For example,at least one cache line of the plurality of cache lines CL1 to CLm maybe selected by an address provided from the processor 1110, and anaccess operation may be performed on the selected cache line.

Each of the plurality of cache sets CS1 to CSn may be selected orrecognized by at least a portion (e.g., a partial address) of theaddress provided from the processor 1110. At least one cache set of theplurality of cache sets CS1 to CSn may be selected by at least a portionof the address provided from the processor 1110, and an access operationmay be performed on the selected cache set.

The tag TAG may include at least a portion of the address provided fromthe processor 1110 or the remaining portion thereof. For example, thecase where at least one of the plurality of cache sets CS1 to CSn isselected by the address or by at least a portion of the address and theaddress is included in the tag TAG of the selected cache set may bedetermined as a cache hit. Alternatively, the case where at least one ofthe plurality of cache sets CS1 to CSn is selected by at least a portionof the address and the address is not included in the tag TAG of theselected cache set may be determined as a cache miss.

FIGS. 3A to 3C are diagrams illustrating an operation of an electronicdevice. For brevity of drawing and convenience of description, it isassumed that the cache memory device 1120 includes first to third cachestorage spaces for storing the first to third cache sets CS1 to CS3,respectively, and the memory device 1200 includes first to third memorystorage spaces for storing the first to third cache lines CL1 to CL3.Hereinafter, the cache sets CS1 to CS3 refer to the cache storage spacesof the cache memory device 1120, unless otherwise described, the cachelines CL1 to CL3 refer to the memory storage spaces of the memory device1200, unless otherwise described. Also, it is assumed that the firstcache line CL1 corresponds to the first cache set CS1, the second cacheline CL2 corresponds to the second cache set CS2, and the third cacheline CL3 corresponds to the third cache set CS3. For example, the firstcache set CS1 may be associated with the first cache line CL1 to storedata thereof, the second cache set CS2 may be associated with the secondcache line CL2 to store data thereof, and the third cache set CS3 may beassociated with the third cache line CL3 to store data thereof. It isassumed that sector data A1, A2, A3, and A4 are stored in the firstcache line CL1 and sector data B1, B2, B3, and B4 are stored in thethird cache line CL3. However, the present disclosure is not limitedthereto.

Referring to FIGS. 1, 2, and 3A, the processor 1110 may perform the linefill operation such that data in the third cache line CL3 of the memorydevice 1200 are stored in the third cache set CS3 of the cache memorydevice 1120. In an embodiment, the plurality of sector data B1, B2, B3,and B4 of the third cache line CL3 may be stored in the third cache setCS3. The line fill operation from the third cache line CL3 to the thirdcache set CS3 is performed on third cache set CS3 with the valid bit “V”of the first logical value indicating the deactivated state. After theline fill operation, the valid bit “V” of the third cache set CS3 maychange to the second logical value indicating the activated state, andthe dirty bit “D” of the third cache set CS3 may be set to the firstlogical value. The third tag TAG3 of the third cache set CS3 may storeaddress information of the third cache line CL3. For example, the thirdtag TAG3 of the third cache set CS3 may store address information of thethird cache line CL3, which corresponds to the memory address of thethird cache line CL3 where the plurality of sector data B1, B2, B3, andB4 are stored in the memory device 1200. In an embodiment, the addressinformation of the third cache line CL3 stored in the third tag TAG3 ofthe third cache set CS3 may be part of the memory address of the thirdcache line CL3, which may be a block address of the plurality of sectordata B1, B2, B3, and B4.

However, in the line fill operation from the memory device 1200 to thecache memory device 1120, an interface error may occur to data which aretransmitted from the memory device 1200 to the cache memory device 1120,or a cache memory error may occur while data are stored in the cachememory device 1120.

In an embodiment, the processor 1110 may perform the line fill operationsuch that data in the first cache line CL1 of the memory device 1200 arestored in the first cache set CS1 of the cache memory device 1120. Afterthe line fill operation, the first cache set CS1 may store a pluralityof sector data A1, A2′, A3, and A4 in which the sector data A2′ areassumed to be damaged due to such interface or cache memory error, andthe sector data A1, A2′, A3, and A4 stored in the first cache set CS1 ofthe cache memory device 1120 are different from the sector data A1, A2,A3, and A4 stored in the cache line of the memory device 1200. Forbrevity of description, it is assumed that the second sector data A2 ofthe first cache line CL1 may be damaged due to the interface or cachememory error, and may be stored as the second damaged sector data A2′.In an embodiment, the line fill operation from the first cache line CL1to the first cache set CS1 is performed on the first cache set CS1 withthe valid bit “V” of the first logical value indicating the deactivatedstate. After the line fill operation, the valid bit “V” of the firstcache set CS1 may change to the second logical value indicating theactivated state, and the dirty bit “D” of the first cache set CS1 may beset to the first logical value. The first tag TAG1 of the first cacheset CS1 may store address information of the first cache line CL1. Forexample, the first tag TAG1 of the first cache set CS1 may store addressinformation of the first cache line CL3, which corresponds to the memoryaddress of the first cache line CL1 where the plurality of sector dataA1, A2, A3, and A4 are stored in the memory device 1200. In anembodiment, the address information of the first cache line CL1 storedin the first tag TAG1 of the first cache set CS1 may be part of thememory address of the first cache line CL1, which may be a block addressof the plurality of sector data A1, A2, A3, and A4.

Referring to FIG. 3B, the processor 1110 may perform a write operationof the write-back manner. The processor 1110 may transmit a writerequest for a first address ADDR1 indicating the third sector S3 of thefirst cache line CL1 to the cache memory device 1120. In an embodiment,the processor 1110 may transmit the write request including the firstaddress ADDR1 and sector data A3′ to the cache memory device 1120.

The cache memory device 1120 may compare the first address ADDR1 and thefirst tag TAG1 and may determine whether data corresponding to the firstaddress ADDR1 are stored in the first cache set CS1. When the first tagTAG1 indicates a memory address of the first cache line CL1, the cachememory device 1120 may determine that a cache hit occurs. The cachememory device 1120 may store the sector data A3′ in the third sector S3of the first cache set CS1 of the cache memory device 1120.

In response to the determination of the cache hit, the cache memorydevice 1120 may set the dirty bit “D” of the first cache set CS1 to thesecond logical value. The sector data A3 stored in the first cache setCS1 are updated after the line fill operation from the memory device1200 to the cache memory device 1120, and the dirty bit “D” of the firstcache set CS1 may be set to the second logical value which indicatesthat the cached data stored therein is in a dirty state.

Referring to FIG. 3C, when a flush request for a second address ADDR2indicating the first cache line CL1 is received from the processor 1110or when it is determined through an internal operation of the cachememory device 1120 that a flush operation is required, the cache memorydevice 1120 may perform the flush operation on the first cache set CS1.For example, a flush operation may be performed to write cached data ofthe first cache set CS1 to the memory device 1200. After the writeoperation of the write-back manner is performed, the cached data of thefirst cache set CS1 may be different from the data stored in the firstcache line CL1, accessed with the second address ADDR2, of the memorydevice 1200. The flush operation may be performed to update the datastored in the first cache line CL1 of the memory device 1200 with thecached data of the first cache set CS1. The flush operation may betriggered in response to a flush request of the processor 1110 whichdetermines that an application program running on the processor 1110demands the data stored in the second address ADDR2 of the first cacheline CL1 or which is informed from another processor (or another masterother than the processor 1110) that it will access the first cache lineCL1 to retrieve the data stored therein, for example. Since the datastored in the first cache set CS1 of the cache memory 1120, associatedwith the first cache line CL1 of the memory device 1200, is updated inthe previous write operation of the write-back manner, the data of thefirst cache line CL1 needs update using the cached data stored in thefirst cache set CS1 before the application program or another processoraccess to the first cache line CL1 accessed using the second addressADDR2. In an embodiment, the flush operation may be triggered accordingto an internal operation of the cache memory device 1120 based on acache management algorithm. In an embodiment, because the number ofcache sets of the cache memory device 1120 is limited, the flushoperation may be periodically or in response to a cache miss, performedfor a new cache line fill operation.

The cache memory device 1120 may select a victim cache set among aplurality of cache sets for the purpose of performing the flushoperation. In an embodiment, assuming that the first cache set CS1 isselected as a victim cache set, the cache memory device 1120 maydetermine whether the first cache set CS1 is in the dirty state or theclean state. Because the dirty bit “D” of the first cache set CS1 hasthe second logical value, the cache memory device 1120 may determinethat the first cache set CS1 is in a dirty state. In an embodiment, thecache memory device 1120 may select the first cache set CS1 as a victimcache set among a plurality of cache sets, and the flush operation isperformed on the first cache set CS1. For example, when the addressinformation stored in the first TAG1 of the first cache set CS1 ismatched with the second address ADDR2 of the flush request, the flushrequest for the second address ADDR2 is issued to the cache memorydevice 1120.

The cache memory device 1120 may perform the flush operation on thefirst cache set CS1. The cache memory device 1120 may transmit a writerequest for the second address ADDR2 indicated by the first tag TAG1 anda plurality of sector data A1, A2′, A3′, and A4 stored in the firstcache set CS1 to the memory device 1200.

In response to the write request of the flush operation, the memorydevice 1200 may store the plurality of sector data A1, A2′, A3′, and A4in the first cache line CL1 that the second address ADDR2 indicates. Thesecond damaged sector data A2′ may be stored in the first cache lineCL1. Under the condition that only the third sector S3 of the firstcache set CS1 is updated and the second sector S2 of the first cache setCS1 is not updated, in the case where all the sector data A1, A2′, A3′,and A4 stored in the first cache set CS1 are again stored in the memorydevice 1200, damaged data may be stored in the memory device 1200. Thismay cause a system error.

FIG. 4 is a diagram for describing a cache set according to anembodiment of the present disclosure. Referring to FIGS. 2 and 4 , acache set may include a cache line and a cache entry. The cache entrymay include a valid bit “V”, a dirty bit map (D1, D2, D3, D4), and a tagTAG. A cache line may include N sectors (N being a positive number), andthe dirty bit map may include N dirty bits corresponding to the Nsectors, respectively. For brevity of drawing and convenience ofdescription, it is assumed that a dirty bit map includes first to fourthdirty bits D1 to D4 and a cache line includes first to fourth sectors S1to S4. However, the present disclosure is not limited thereto.

The first to fourth dirty bits D1 to D4 may correspond to the first tofourth sectors S1 to S4, respectively. For example, the first dirty bitD1 may indicate dirty information about the first sector S1, the seconddirty bit D2 may indicate dirty information about the second sector S2,the third dirty bit D3 may indicate dirty information about the thirdsector S3, and the fourth dirty bit D4 may indicate dirty informationabout the fourth sector S4. The tag TAG, the valid bit “V”, and thefirst to fourth sectors S1 to S4 are described with reference to FIG. 2, and thus, additional description will be omitted to avoid redundancy.

FIGS. 5A to 5C are diagrams illustrating an operation of an electronicdevice of FIG. 1 . For brevity of drawing and convenience ofdescription, it is assumed that the cache memory device 1120 includesthe first to third cache sets CS1 to CS3, and the memory device 1200includes the first to third cache lines CL1 to CL3. For the sake ofdescription, it is assumed that the first cache line CL1 corresponds tothe first cache set CS1, the second cache line CL2 corresponds to thesecond cache set CS2, and the third cache line CL3 corresponds to thethird cache set CS3. It is assumed that the sector data A1, A2, A3, andA4 are stored in the first cache line CL1, and the sector data B1, B2,B3, and B4 are stored in the third cache line CL3. However, the presentdisclosure is not limited thereto.

The processor 1110 may perform the line fill operation on the thirdcache line CL3. The line fill operation associated with the third cacheline CL3 is described with reference to FIG. 3A, and thus, additionaldescription will be omitted to avoid redundancy. However, because dirtyinformation is managed in units of sector, each of the first to fourthdirty bits D1 to D4 of the third cache set CS3 may be initialized to thefirst logical value, and, depending on whether cached data associatedwith each of the first to fourth dirty bits D1 to D4 are updated, maychange to the second logical value.

In the line fill operation from the memory device 1200 to the cachememory device 1120, the cached data stored in the first to third cachesets CS1, CS2, and CS3 may have the interface or cache memory error.

In an embodiment, the processor 1110 may perform the line fill operationsuch that data in the first cache line CL1 of the memory device 1200 arestored in the first cache set CS1 of the cache memory device 1120. Asdescribed with reference to FIG. 3A, the plurality of sector data A1,A2′, A3, and A4 may be stored in the first cache set CS1. This isdescribed above, and thus, additional description will be omitted toavoid redundancy. However, the first to fourth dirty bits D1 to D4 ofthe first cache set CS1 may be initialized to the first logical value,and, depending on whether cached data associated with each of the firstto fourth dirty bits D1 to D4 are updated, may change to the secondlogical value.

Referring to FIG. 5B, the processor 1110 may perform a write operationof the write-back manner. The processor 1110 may transmit a writerequest for the first address ADDR1 indicating the third sector S3 ofthe first cache line CL1 to the cache memory device 1120. In anembodiment, the processor 1110 may transmit the write request includingthe first address ADDR1 and the sector data A3′ to the cache memorydevice 1120. The cache memory device 1120 may store the sector data A3′in the third sector S3 of the first cache set CS1.

The cache memory device 1120 may set the third dirty bit D3 of the firstcache set CS1 to the second logical value. For example, the third sectorS3 of the first cache set CS1 is updated after the line fill operationfrom the memory device 1200 to the cache memory device 1120, and thedirty bit D3 of the first cache set CS1 associated with the sector S3 ofthe third cache set CS1 may be set to the second logical level thatindicates that the cached data stored therein is in a dirty state.

Referring to FIG. 5C, when the flush request for the second addressADDR2 indicating the first cache line CL1 is received from the processor1110 or when it is determined through an internal operation of the cachememory device 1120 that the flush operation is required, the cachememory device 1120 may perform the flush operation on the first cacheset CS1.

The cache memory device 1120 may transmit the write request for thesecond address ADDR2 indicated by the first tag TAG1, a plurality ofsector data A1, A2′, A3′, and A4 stored in the first cache set CS1, andthe dirty information DI to the memory controller 1130.

The dirty information DI may include the dirty bit map or the first tofourth dirty bits D1 to D4. The first to fourth dirty bits D1 to D4 ofthe dirty information DI may correspond to the first to fourth dirtybits D1 to D4 of the first cache set CS1, respectively. In theembodiment of FIG. 5B, the first dirty bit D1, the second dirty bit D2,and the fourth dirty bit D4 of the dirty information DI may have thefirst logical value indicating that their associated cached data storedin the first cache set CS1 is in the clean state, and the third dirtybit D3 of the dirty information DI may have the second logical valueindicating that its associated cached data stored in the first cache setCS1 is in the dirty state.

The data mask control circuit 1131 of the memory controller 1130 mayreceive the dirty information DI. The memory controller 1130 maygenerate the data mask signal DM in response to the second addressADDR2, the plurality of sector data A1, A2′, A3′, and A4, and the dirtyinformation DI. In an embodiment, because the first dirty bit D1, thesecond dirty bit D2, and the fourth dirty bit D4 of the dirtyinformation DI have the first logical value indicating the clean state,the data mask signal DM corresponding to the first sector data A1, thesecond sector data A2′, and the fourth sector data A4 may have thesecond logical value indicating an activated state in which sector dataassociated with the data mask signal DM having the second logical valueare masked. Because the third dirty bit D3 of the dirty information DIhas the second logical value indicating the dirty state, the data masksignal DM corresponding to the third sector data A3′ may have the firstlogical value indicating a deactivated state in which sector dataassociated with the data mask signal DM having the logical value arestored in the memory device 1200. The memory controller 1130 maytransmit the data mask signal DM to the memory device 1200 through thedata mask line. This will be more fully described with reference to thefollowing drawing.

In response to the write request of the flush operation, the cached dataof the first cache set CS1 may be selectively stored in the memorydevice 1200 based on the data mask signal DM. For example, because thedata mask signal DM corresponding to the first, second, and fourthsector data A1, A2′, and A4 has the second logical value indicating theactivated state, the first sector data A1, the second sector data A2′,and the fourth sector data A4 of the cached data stored in the firstcache set CS1 are not stored in the memory device 1200. For example,based on the data mask signal DM, the data stored in the memory device1200 are not updated with the first, second, and fourth sector data A1,A2′, and A4 of the cached data of the first cache set CS1 in the flushoperation, or the first, second, and fourth sector data A1, A2′, and A4of the cached data stored in the first cache set CS1 may be blocked ormasked in the flush operation. Masking may indicate that that cacheddata associated with the data mask signal DM indicating that a datamasking operation is activated are not stored or written in the memorydevice 1200. As such, the second damaged sector data A2′ of the firstcache set CS1 are not stored in the memory device 1200. The data masksignal DM associated with the third sector data A3′ has the firstlogical value indicating that a data masking operation is deactivated,the third sector data A3′ of the cached data stored in the first cacheset CS1 may be stored, without being masked by a data masking operation,in the memory cell array of the memory device 1200.

As described above, according to an embodiment of the presentdisclosure, in the electronic device 1000 performing the write operationof the write-back manner, each cache set may include storage spaces forstoring a plurality of dirty bits associated with a plurality ofsectors. As the electronic device 1000 manages a dirty bit in units ofsector smaller than a cache line, the electronic device 1000 maydetermine a clean state or a dirty state for each sector. The cachememory device 1120 may transmit the dirty information DI to the memorycontroller 1130. The memory controller 1130 may generate the data masksignal DM based on the dirty information DI. The memory device 1200 mayreceive the data mask signal DM through the data mask line. In a flushoperation, the memory device 1200 may selectively store cached data inthe memory device 1200 based on the data mask signal DM.

In the line fill operation from the memory device 1200 to the cachememory device 1120 is performed, data may be damaged due to an interfaceor cache memory error, and the damaged data may be stored in the cachememory device 1120. Afterwards, when the damaged data may be flushed tothe memory device 1200, the damaged data may be masked such that theinterface or cache memory error of the damaged data is not propagated tothe memory device 1200.

The electronic device 1000 according to an embodiment of the presentdisclosure may store data in the memory device 1200 in units of sectorbased on the dirty information DI and the data mask signal DM, and thus,some of the cache data corresponding to sector data are not updated in acache operation, and are not stored in the memory device 1200 in a flushoperation. Accordingly, the amount of current consumption in a flushoperation may decrease, and power consumption of the electronic device1000 is minimized. An improved electronic device may be provided.

FIG. 6 is a flowchart illustrating an operation of a memory controllerof FIG. 1 . For convenience of description, it is assumed that thememory controller 1130 exchanges data through first to sixteenth datalines DQ1 to DQ16. Also, it is assumed that the memory controller 1130includes one data mask line for the first to sixteenth data lines DQ1 toDQ16 (see, FIG. 1 ). However, the present disclosure is not limitedthereto.

For convenience of description, it is assumed that a size of one cacheline is 64 Bytes. However, the present disclosure is not limitedthereto. In an embodiment, it is assumed that a burst length BL is setto 32 (BL=32) to transmit data corresponding to a cache line through thefirst to sixteenth data lines DQ1 to DQ16. For example, the datacorresponding to the cache line may be a cached data stored in a cacheset associated with the cache line, and the data transmission from thecache memory device 1120 to the memory device 1200 may be achieved byperforming a write operation with a burst length of 32, for example, onthe memory device 1200.

Referring to FIGS. 5C and 6 , in operation S100, the memory controller1130 may receive a write request from the processor 1110. For example,the write request may be issued in a flush operation. In an embodiment,the memory controller 1130 may receive an address, a write request (or awrite command) including the dirty information DI, and write data“DATA”. The dirty information DI may include the first to fourth dirtybits D1 to D4 or the dirty bit map. The write data “DATA” may includethe first to fourth sector data A1, A2′, A3′, and A4. In an embodiment,the write data “DATA” may correspond to cached data stored in the cachememory device.

In operation S200, the memory controller 1130 may sequentially arrangethe write data “DATA” (e.g., 64 Bytes) in 32 rows, each row having 16bits which will be outputted using the first to sixteenth data lines DQ1to DQ16 in each burst operation. In a burst operation with the burstlength BL (=32), 16 bits are outputted 32 times via the first tosixteenth data lines DQ1 to DQ16. For example, the memory controller1130 may arrange the first sector data A1 so as to be output through thedata lines DQ1 to DQ16 during first to eight burst lengths, may arrangethe second sector data A2′ so as to be output through the data lines DQ1to DQ16 during ninth to sixteenth burst lengths, may arrange the thirdsector data A3′ so as to be output through the data lines DQ1 to DQ16during seventeenth to twenty fourth burst lengths, and may arrange thefourth sector data A4 so as to be output through the data lines DQ1 toDQ16 during twenty fifth to thirty burst lengths.

The write data “DATA” may include first to thirty-second input dataDin_1 to and Din_32. In an embodiment, the write data “DATA” may includethe first input data Din_1 to be transmitted to the data lines DQ1 toDQ16 during the first burst length, the second input data Din_2 to betransmitted to the data lines DQ1 to DQ16 during the second burstlength, the third input data Din_3 to be transmitted to the data linesDQ1 to DQ16 during the third burst length, and the fourth input dataDin_4 to be transmitted to the data lines DQ1 to DQ16 during the fourthburst length. The remaining input data Din_5 to Din_32 are similar tothe input data Din_1 to Din_4 in structure, and thus, additionaldescription will be omitted to avoid redundancy.

That is, the first sector data A1 may correspond to the first to eighthinput data Din_1 to Din_8, the second sector data A2′ may correspond tothe ninth to sixteenth input data Din_9 to Din_16, the third sector dataA3′ may correspond to the seventeenth to twenty-fourth input data Din_17to Din_24, and the fourth sector data A4 may correspond to thetwenty-fifth to thirty-third input data Din_25 to Din_32.

In operation S300, the memory controller 1130 may generate the data masksignal DM based on the dirty information DI. The data mask signal DM mayinclude the first to thirty-second data mask signals DM1 to DM32corresponding to the burst length BL (=32) so that each burst operationmay be masked using a corresponding data mask signal of the first tothirty-second data mask signals DM1 to DM32. The data mask signals DM1to DM32 may correspond to the plurality of input data Din_1 to Din_32,respectively. For example, the first data mask signal DM1 may indicatemask information about the first input data Din_1, the second data masksignal DM2 may indicate mask information about the second input dataDin_2, the third data mask signal DM3 may indicate mask informationabout the third input data Din_3, and the fourth data mask signal DM4may indicate mask information about the fourth input data Din_4. Theremaining data mask signals DM5 to DM32 are similar to the data masksignals DM1 to DM4 in structure, and thus, additional description willbe omitted to avoid redundancy.

In an embodiment, when a dirty bit of the dirty information DI has thefirst logical value, because the corresponding cached data stored in thecache memory 1120 is in the clean state, the corresponding cached dataare not stored in the memory device 1200. For example, the memory device1200 may mask the corresponding cached data which is in the clean state.In response to the dirty information DI, the memory controller 1130 mayset the data mask signal DM to the second logical value indicating thata data masking operation is in the activated state. When a dirty bit ofthe dirty information DI has the second logical value, the correspondingcached data is in the dirty state, and the corresponding cached data maybe stored in the memory device 1200. The memory controller 1130 may setthe data mask signal DM to the first logical value indicating that adata masking operation is in the deactivated state. A method ofgenerating a data mask signal will be more fully described withreference to FIG. 7 .

In operation S400, the memory controller 1130 may output the write data“DATA” and the data mask signal DM in synchronization with the datastrobe signal DQS in a mask write operation MWR. In an embodiment, thememory controller 1130 may transmit write data through the data linesDQ1 to DQ16 in response to the data strobe signal DQS. For example, thememory controller 1130 may generate the data strobe signal DQS and mayoutput write data through the data lines DQ1 to DQ16 in synchronizationwith the data strobe signal DQS. The memory controller 1130 may outputthe data mask signal DM through a data mask line in synchronization withthe data strobe signal DQS.

FIG. 7 is a timing diagram illustrating operation S400 of FIG. 6 indetail. Referring to FIGS. 1 and 7 , the memory controller 1130 mayoutput write data and the data mask signal DM in synchronization withthe data strobe signal DQS. In an embodiment, the memory controller 1130may transmit write data through the data lines DQ1 to DQ16 based on thedata strobe signal DQS. For example, the memory controller 1130 mayoutput write data through the data lines DQ1 to DQ16 in synchronizationwith a rising edge and a falling edge of the data strobe signal DQS. Thememory controller 1130 may also output the data mask signal DM through adata mask line in synchronization with the data strobe signal DQS.

In an embodiment, referring to FIG. 5C, it is assumed that the dirtyinformation DI includes the first dirtybit D1 of the first logicalvalue, the second dirtybit D2 of the first logical value, the thirddirtybit D3 of the second logical value, and the fourth dirtybit D4 ofthe first logical value. It is assumed that a plurality of sector dataA1, A2′, A3′, and A4 are to be transmitted to the memory device 1200.However, the present disclosure is not limited thereto. As describedabove, the first logical value may mean the clean state representingthat its associated cached data has not been changed since the data wereuploaded to the cache memory device from the memory device, and thesecond logical value may mean the dirty state representing that itsassociated cached data has changed after being uploaded.

Because the first dirty bit D1 of the dirty information DI has the firstlogical value, the first sector data A1 stored in the cache memory 1120are not stored in the memory device 1200; because the second dirty bitD2 of the dirty information DI has the first logical value, the secondsector data A2′ stored in the cache memory 1120 are not stored in thememory device 1200; because the third dirty bit D3 of the dirtyinformation DI has the second logical value, the third sector data A3′stored in the cache memory 1120 are stored in the memory device 1200;and, because the fourth dirty bit D4 of the dirty information DI has thefirst logical value, the fourth sector data A4 are not stored in thememory device 1200.

For example, the masking of the first to eighth input data Din_1 toDin_8 corresponding to the first sector data A1 may be activated, themasking of the ninth to sixteenth input data Din_9 to Din_16corresponding to the second sector data A2′ may be activated, themasking of the seventeenth to twenty-fourth input data Din_17 to Din_24corresponding to the third sector data A3′ may be deactivated, and themasking of the twenty-fifth to thirty-second input data Din_25 to Din_32corresponding to the fourth sector data A4 may be activated.

For example, the first to eighth data mask signals DM1 to DM8respectively corresponding to the first to eighth input data Din_1 toDin_8 may have the second logical value, the ninth to sixteenth datamask signals DM9 to DM16 respectively corresponding to the ninth tosixteenth input data Din_9 to Din_16 may have the second logical value,the seventeenth to twenty-fourth data mask signals DM17 to DM24respectively corresponding to the seventeenth to twenty-fourth inputdata Din_17 to Din_24 may have the first logical value, and thetwenty-fifth to thirty-second data mask signals DM25 to DM32respectively corresponding to the twenty-fifth to thirty-second inputdata Din_25 to Din_32 may have the second logical value.

In an embodiment, the first logical value corresponds to a logic lowlevel, and the second logical value corresponds to a logic high level.The data mask signal DM may be at the logic high level during a firsttime period T1, may be at the logic high level during a second timeperiod T2, may be at the logic low level during a third time period T3,and may be at the logic high level during a fourth time period T4.

In an embodiment, the data mask signal DM may correspond to a data mask(DM_n) signal which is specified in the DDR 4.0 specification. Theelectronic device 1000 may activate or deactivate a data mask functionby setting a mode register. The electronic device 1000 may activate ordeactivate the data mask function through a tenth address A10 of a fifthmode register MR5. The electronic device 1000 may deactivate the datamask function by setting the tenth address A10 of the fifth moderegister MR5 to “0” and may activate the data mask function by settingthe tenth address A10 of the fifth mode register MR5 to “1”.

In an embodiment, referring to FIG. 5C, the memory controller 1130 mayreceive the dirty information DI that includes the first dirty bit D1 ofthe first logical value, the second dirty bit D2 of the first logicalvalue, the third dirty bit D3 of the second logical value, and thefourth dirty bit D4 of the first logical value. The memory controller1130 may transmit the DM_n signal based on the dirty information DI.

For example, the memory controller 1130 may mask the first to eighthinput data Din_1 to Din_8 by setting the DM_n signal to the logic lowlevel during the first time period T1, may mask the ninth to sixteenthinput data Din_9 to Din_16 by setting the DM_n signal to the logic lowlevel during the second time period T2, may not mask the seventeenth totwenty-fourth input data Din_17 to Din_24 by setting the DM_n signal tothe logic high level during the third time period T3, and may mask thetwenty-fifth to thirty-second input data Din_25 to Din_32 by setting theDM_n signal to the logic low level during the fourth time period T4.

FIG. 8 is a block diagram illustrating a memory device of FIG. 1 indetail. Referring to FIGS. 1 and 8 , the memory device 1200 may includea memory cell array 1210, a row decoder 1220, a column decoder 1230, acontrol logic circuit 1240, and an input/output circuit 1250.

The memory cell array 1210 may include a plurality of memory cells. Eachof the plurality of memory cells may be a DRAM cell including a storagecapacitor and a transistor, but the present disclosure is not limitedthereto. The plurality of memory cells may be connected with a pluralityof word lines and a plurality of bit lines.

The row decoder 1220 may select at least one word line of the pluralityof word lines under control of the control logic circuit 1240 and maydrive the selected word line. The column decoder 1230 may select atleast one bit line of the plurality of bit lines under control of thecontrol logic circuit 1240 and may drive the selected bit line.

The control logic circuit 1240 may receive the address ADDR, the commandCMD, and the control signal CTRL from the memory controller 1130 and maycontrol components of the memory device 1200 based on the receivedsignals. The control logic circuit 1240 may receive the data mask signalDM from the memory controller 1130 through the data mask line.

The control logic circuit 1240 may selectively store data in the memorycell array 1210 based on the data mask signal DM. In an embodiment, whenthe data mask signal DM has the first logical value, the control logiccircuit 1240 may store the corresponding input data in the memory cellarray 1210. When the data mask signal DM has the second logical value,the control logic circuit 1240 does not store the corresponding inputdata in the memory cell array 1210.

The input/output circuit 1250 may receive the write data “DATA” from thememory controller 1130 through the data lines DQ1 to DQ16, together withthe data strobe signal DQS.

As described above, in the electronic device 1000 according to anembodiment of the present disclosure, a dirty bit may be managed inunits of sector smaller in size than a cache line, dirty information maybe provided to a memory controller, and a memory device may selectivelystore data based on the data mask signal DM. As a result, the stabilityof system may be improved, and power consumption may be minimized.

FIGS. 9A and 9B are timing diagrams for describing an operation of amemory device of FIG. 1 . A mask write (MWR) operation will be describedwith reference to FIGS. 9A and 9B. The MWR operation may correspond tovarious operations that are supported through various standardinterfaces, which are defined by the Joint Electron Device EngineeringCouncil (JEDEC) standard, such as a Low-Power Double Data Rate (LPDDR)DRAM standard, a Double Data Rate (DDR) DRAM standard, and a Graphic DDR(GDDR) standard. Referring to FIGS. 1 and 9 , the electronic device 1000may perform the mask write operation based on the timing diagramillustrated in FIG. 9 .

The electronic device 1000 may perform the data mask function and a databus inversion (DBI) function through the DMI signal. The electronicdevice 1000 may activate or deactivate each of the data mask functionand the data bus inversion function by setting a mode register. Theelectronic device 1000 may activate or deactivate the data bus inversionfunction through a seventh operation code OP[7] of a third mode registerMR3. The electronic device 1000 may activate or deactivate the data maskfunction through a fifth operation code OP[5] of a thirteenth moderegister MR13.

The electronic device 1000 may activate the data bus inversion functionby setting the seventh operation code OP[7] of the third mode registerMR3 to “1” and may deactivate the data bus inversion function by settingthe seventh operation code OP[7] to “0”. The electronic device 1000 mayactivate the data mask function by setting the fifth operation codeOP[5] of the thirteenth mode register MR13 to “0” and may deactivate thedata mask function by setting the fifth operation code OP[5] to “1”.

First, it will be described that when the data mask function isactivated, and the data bus inversion function is deactivated, how theMWR operation is implemented. In an embodiment, the data mask inversion(DMI) signal is used as a data mask signal as discussed above withreference to FIGS. 1 through 7 . For example, the memory controller 1130may transmit a burst length BL through a command/address signal CA at afirst time t1, and may transmit a bank address BA, a column address CA,and an auto-precharge AP through the command/address signal CA at asecond time t2. The burst length BL, the bank address BA, the columnaddress CA, and the auto-precharge AP transmitted at the first andsecond times t1 and t2 may constitute a first MWR command MWR-1. In anembodiment, the burst length BL included in the first MWR command MWR-1and the bank address BA, the column address CA, and the auto-prechargeAP included in the first MWR command MWR-1 may be distinguished fromeach other by setting a chip select signal CS to the logic high level atthe first time t1 and setting the chip select signal CS to the logic lowlevel at the second time t2.

Immediately after the first MWR command MWR-1 is transmitted, theelectronic device 1000 may transmit column addresses CAn through thecommand/address signal CA at a third time t3 and a fourth time t4,respectively. The two column addresses CAn may constitute a second CAScommand CAS-2. In an embodiment, the two column addresses CAn includedin the second CAS command CAS-2 may be distinguished from each other bysetting the chip select signal CS to the logic high level at the thirdtime t3 and setting the chip select signal CS to the logic low level atthe fourth time t4.

In an embodiment, Table 1 below shows a command truth table of the firstMWR command MWR-1 and the second CAS command CAS-2, which are based onthe protocol of the LPDDR 4.0 specification.

TABLE 1 CS CA0 CA1 CA2 CA3 CA4 CA5 CK_t MRW-1 H L L H H L L R1 L BA0 BA1BA2 V C9 AP R2 CAS-2 H L H L L H C8 R1 L C2 C3 C4 C5 C6 C7 R2

As shown in Table 1 above, the first MWR command MWR-1 and the secondCAS command CAS-2 may be transmitted by controlling the chip selectsignal CS and a plurality of command/address signals CA. For example,the command/address signal CA may include the 0-th to fifthcommand/address signals CA0 to CA5. The memory controller 1130 maytransmit a first portion of the first MWR command MWR-1 by setting thechip select signal CS, and second and third command/address signals CA2and CA3 to “H” (high), and setting 0-th, first, fourth, and fifthcommand/address signals CA0, CA1, CA4, and CA5 to “L” (low), at a firstrising edge R1 of the clock signal CK_t (e.g., at the first time t1).The memory controller 1130 may transmit a second portion of the firstMWR command MWR-1 by setting the chip select signal CS to “L” andsetting 0-th to second bank addresses BA0 to BA2 as the 0-th to secondcommand/address signals CA0 to CA2, respectively, setting the fourthcommand/address signal CA4 as a ninth column address C9, and setting thefifth command/address signal CA5 as the auto-precharge AP, at a secondrising edge R2 of the clock signal CK_t (e.g., at the second time t2).For example, the memory controller 1130 may transmit the first MWRcommand MWR-1 by setting the chip select signal CS and the plurality ofcommand/address signals CA0 to CA5 at two rising edges R1 and R2 of theclock signal CK_t according to the command truth table as shown in Table1 above. Likewise, the memory controller 1130 may transmit a firstportion of the second CAS command CAS-2 by setting the chip selectsignal CS and the first and fourth command/address signals CA1 and CA4to “H”, setting the 0-th, second, and third command/address signals CA0,CA2, and CA3 to “L”, and setting an eighth column address C8 as thefifth command/address signal CA5, at the first rising edge R1 of theclock signal CK_t (e.g., at the third time t3) after the first MWRcommand MWR-1 is transmitted. Afterwards, the memory controller 1130 maytransmit a second portion of the second CAS command CAS-2 by setting thechip select signal CS to “L” and setting second to seventh columnaddresses C2 to C7 as the 0-th to fifth command/address signals CA0 toCA5, respectively. For example, the memory controller 1130 may transmitthe second CAS command CAS-2 by setting the chip select signal CS andthe plurality of command/address signals CA0 to CA5 at two rising edgesR1 and R2 of the clock signal CK_t according to the command truth tableas shown in Table 1 above.

In an embodiment, the data strobe signal DQS may start to be toggledafter a write latency WL passes from a time t4 at which the second CAScommand CAS-2 is transmitted. Input data may be transmitted through datalines DQ in synchronization with the data strobe signal DQS. The datamask inversion signal DMI may be transmitted in synchronization with thedata strobe signal DQS.

In an embodiment, referring to FIG. 5C, the memory controller 1130 mayreceive the dirty information DI that includes the first dirty bit D1 ofthe first logical value, the second dirty bit D2 of the first logicalvalue, the third dirty bit D3 of the second logical value, and thefourth dirty bit D4 of the first logical value. The memory controller1130 may transmit the DMI signal based on the dirty information DI.

For example, the memory controller 1130 may mask the first to eighthinput data Din_1 to Din_8 by setting the DMI signal, which is used asthe data mask signal as described above with reference to FIGS. 1through 7 , to the logic high level during the first time period T1, maymask the ninth to sixteenth input data Din_9 to Din_16 by setting theDMI signal to the logic high level during the second time period T2, maynot mask the seventeenth to twenty-fourth input data Din_17 to Din_24 bysetting the DMI signal to the logic low level during the third timeperiod T3, and may mask the twenty-fifth to thirty-second input dataDin_25 to Din_32 by setting the DMI signal to the logic high levelduring the fourth time period T4.

It will be described that when both the data mask function and the databus inversion function are activated, how the MWR operation isimplemented with reference to FIG. 9B. The first MWR command MWR-1 andthe second CAS command CAS-2 are more fully described above, and thus,additional description will be omitted to avoid redundancy.

Because the data bus inversion function is activated, the case where theDMI signal is at the logic high level may indicate that thecorresponding data are inverted, and the case where the DMI signal is atthe logic low level may indicate that the corresponding data are notinverted. That is, unlike FIG. 9A, when the data bus inversion functionis activated, the memory controller 1130 does not use the DMI signal inthe data mask function. Instead, the memory controller 1130 may transmitmasked write data through the data lines DQ1 to DQ16.

For example, data corresponding to the case where the DMI signal is setto the logic low level and the number of 1's of data bits transmittedthrough the second to seventh data lines DQ2 to DQ7 is 5 or more may beregarded as masked data, or the data corresponding to the case where theDMI signal is set to the logic low level and the number of 1's of databits transmitted through the tenth to fifteenth data lines DQ10 to DQ15is 5 or more may be regarded as masked data.

In an embodiment, referring to FIG. 5C, the memory controller 1130 mayreceive the dirty information DI that includes the first dirty bit D1 ofthe first logical value, the second dirty bit D2 of the first logicalvalue, the third dirty bit D3 of the second logical value, and thefourth dirty bit D4 of the first logical value. The memory controller1130 may generate masked data based on the dirty information DI.

In an embodiment, during the first to fourth time periods T1 to T4, thememory controller 1130 may set the DMI signal to the logic low level.Because the third dirty bit D3 is set to the second logical value, datacorresponding to the third dirty bit D3 may not be masked. Theseventeenth to twenty-fourth input data Din_17 to Din_24 may not bechanged. In contrast, because the first, second, and fourth dirty bitsD1, D2, and D4 are set to the first logical value, data corresponding tothe first, second, and fourth dirty bits D1, D2, and D4 may be masked.The first to eighth input data Din_1 to Din_8, the ninth to sixteenthinput data Din_9 to Din_16, and the twenty-fifth to thirty-second inputdata Din_25 to Din_32 may be changed to masked data before transmission.In each of the first, second, and fourth time periods T1, T2, and T4,the number of 1's of data bits transmitted to the second to seventh datalines DQ2 to DQ7 may be at least 5 or more, or the number of 1's of databits transmitted to the tenth to fifteenth data lines DQ10 to DQ15 maybe at least 5 or more.

As described above, the memory controller 1130 may provide input dataand a data mask signal to the memory device 1200 based on the MWRoperation described with reference to FIGS. 9A and 9B.

FIG. 10A is a flowchart illustrating an operation of an electronicdevice of FIG. 1 , according to an embodiment. Referring to FIGS. 1, 2,and 4 , in operation S1010, the processor 1110 may transmit a readrequest including a first address ADDR1 to the cache memory device 1120.The first address ADDR1 may be an address corresponding to a storagespace of the memory device 1200, in which read data are stored.

In operation S1020, in response to the read request, the cache memorydevice 1120 may determine whether data corresponding to the firstaddress ADDR1 are stored in the cache memory device 1120. For example,the cache memory device 1120 may determine whether a cache hit or acache miss occurs, based on the tag TAG. The cache memory device 1120may determine whether a cache hit or a cache miss occurs, based on aresult of comparing the tag TAG and the first address ADDR1 from theprocessor 1110 or a result of comparing the tag TAG and at least aportion of the first address ADDR1.

In an embodiment, the cache memory device 1120 may select cache sets,which include the tags TAG corresponding to the first address ADDR1 or aportion of the first address ADDR1, from among a plurality of cache setsand may read the tags TAG of the selected cache sets. The cache memorydevice 1120 may compare the tag TAG and the first address ADDR1 todetermine whether a cache hit or a cache miss occurs. However, thepresent disclosure is not limited thereto. For example, whether a cachehit or a cache miss occurs may be determined in various methods. When itis determined that a cache hit occurs, in operation S1140, the cachememory device 1120 may transmit first data DATA1 corresponding to thefirst address ADDR1 to the processor 1110.

When it is determined that a cache miss occurs, the cache memory device1120 performs operation S1030. To allocate a new cache set for storingdata corresponding to the first address ADDR1 from the processor 1110,the cache memory device 1120 may select a cache set with a valid bit “V”of the first logical value among the plurality of cache sets. If nocache set with a valid bit “V” of the first logical value remains in thecache memory 1120, one victim cache set may be selected from theplurality of cache sets to be flushed. In an embodiment, the cachememory device 1120 may select a victim cache set, for example, in amanner to select the least recently used cache set (LRU), in a manner toselect the most recently used cache set (MRU), or in a manner to selecta first in first out cache set (FIFO).

In operation S1040, the cache memory device 1120 may determine whetherthe victim cache set is in the dirty state. In an embodiment, when atleast one of the plurality of dirty bits D1 to D4 of the victim cacheset indicates the second logical value, the cache memory device 1120 maydetermine that the victim cache set is in the dirty state. When thevictim cache set is not in the dirty state, that is, in the clean state,in operation S1080, the cache memory device 1120 may transmit cacheinformation INFO including cache miss information without performing theflush operation on the victim cache set. When the victim cache set is inthe dirty state, the cache memory device 1120 performs operation S1050to perform the flush operation on the victim cache set.

In operation S1050, the cache memory device 1120 may transmit the cacheinformation INFO to the processor 1110. In an embodiment, the cacheinformation INFO may include information about the victim cache set.

In operation S1060, the processor 1110 may perform the flush operationassociated with the victim cache set in response to the cacheinformation INFO including the information about the victim cache set.The processor 1110 may transmit a write request to the memory controller1130. In an embodiment, the processor 1110 may transmit the writerequest including an address indicating a cache line of the memorydevice 1200, which corresponds to the victim cache set. The processor1110 may transmit the dirty information DI including the first to fourthdirty bits D1 to D4 of the victim cache set to the memory controller1130. The processor 1110 may transmit cached data of the victim cacheset to the memory controller 1130.

In operation S1070, based on the dirty information DI, the cached data,and a write request including an address, the memory controller 1130 maytransmit the data mask signal DM to the memory device 1200 together withthe cached data of the victim cache set. In an embodiment, the memorycontroller 1130 may receive the write request including the address, thedirty information DI, and the cached data. The memory controller 1130may sequentially arrange the cached data such that the cached data areoutput to the first to sixteenth data lines DQ1 to DQ16 a predeterminednumber (e.g., the burst length) of times. The memory controller 1130 maygenerate the data mask signal DM based on the dirty information DI. Thememory controller 1130 may output the data and the data mask signal DMin synchronization with the data strobe signal DQS. This is describedabove, and thus, additional description will be omitted to avoidredundancy.

In operation S1080, the cache memory device 1120 may transmit the cacheinformation INFO to the processor 1110. In an embodiment, the cacheinformation INFO may include cache miss information about the firstaddress ADDR1.

In an embodiment, when the victim cache set is in the dirty state,operation S1080 may be omitted, and in operation S1050, the cache memorydevice 1120 may transmit the cache information INFO including the cachemiss information about the first address ADDR1. Also, the order ofperforming operation S1030 to operation S1070, and operation S1080 maybe changed, or operation S1030 to operation S1070 may be performed inparallel with operation S1080. The flowchart in FIG. 10A is only oneembodiment, and operation S1020 to operation S1040 may be performed bythe processor 1110.

In operation S1080, in response to the cache information INFO includingthe cache miss information, the processor 1110 may recognize that datacorresponding to the first address ADDR1 are not stored in the cachememory device 1120. In this case, the processor 1110 may transmit a readrequest to the memory controller 1130.

In an embodiment, the processor 1110 may transmit, to the memorycontroller 1130, a read request including a second address ADDR2indicating at least one cache line of the plurality of cache lines CL1to CLm of the memory device 1200. A cache line may be a minimum unit ofdata that the processor 1110 transmits to the memory device 1200 in aread or write request. Accordingly, when the first address ADDR1 doesnot indicate at least one of the plurality of cache lines CL1 to CLm,the processor 1110 may transmit to the memory device 1200 a read requestfor the second address ADDR2 indicating a cache line including the firstaddress ADDR1.

When the first address ADDR1 indicates at least one of the plurality ofcache lines CL1 to CLm, the first address ADDR1 and the second addressADDR2 may be identical. In contrast, when the first address ADDR1 is nota start address of a cache line but indicates any space in the cacheline, the first address ADDR1 and the second address ADDR2 may bedifferent.

In operation S1100, the memory controller 1130 may transmit a readrequest to the memory device 1200. In an embodiment, the memorycontroller 1130 may transmit a command and the second address ADDR2 tothe memory device 1200. In operation S1110, in response to the readrequest, the memory device 1200 may output the second data DATA2 to thememory controller 1130.

In operation S1120, the memory controller 1130 may transmit the seconddata DATA2 received from the memory device 1200 to the cache memorydevice 1120. In operation S1130, the cache memory device 1120 may storethe second data DATA2 in the victim cache set. The cache memory device1120 may initialize the dirty bit D of the victim cache set. Forexample, the cache memory device 1120 may set the plurality of dirtybits D1 to D4 of the victim cache set to the first logical value.

As such, data may be damaged at an interface during a time whenoperation S1100 to operation S1130 are performed, or damaged data may bestored while data are stored in the cache memory device 1120. When theline fill operation from the memory device 1200 to the cache memorydevice 1120 is performed, with regard to the same address, data storedin the memory device 1200 may not be damaged, but damaged data may bestored in the cache memory device 1120.

In operation S1140, the cache memory device 1120 may transmit the firstdata DATA1 corresponding to the first address ADDR1 to the processor1110. The first data DATA1 may be equal to or smaller than a cache linein size. The second data DATA2 may be equal to a cache line in size.

FIG. 10B is a flowchart illustrating an operation of an electronicdevice of FIG. 1 , according to an embodiment. Referring to FIGS. 1, 2,and 4 , in operation S2010, the processor 1110 may transmit a writerequest of a write-back manner including the first address ADDR1 and thefirst data DATA1 to the cache memory device 1120.

In operation S2020, in response to the write request, the cache memorydevice 1120 may determine whether data corresponding to the firstaddress ADDR1 are stored in the cache memory device 1120. The cachememory device 1120 may determine whether a cache hit or a cache missoccurs, based on the tag TAG. This is described with reference to FIG.10A in detail, and thus, additional description will be omitted to avoidredundancy. When it is determined that a cache hit occurs, the methodproceeds to operation S2140. When it is determined that a cache missoccurs, the method proceeds to operation S2030.

Operation S2030 to operation S2130 are identical to operation S1030 tooperation S1130 of FIG. 10A, and thus, additional description will beomitted to avoid redundancy. In operation S2140, the cache memory device1120 may store the first data DATA1 received from the processor 1110.

In an embodiment, in the case of receiving the first data DATA1 equal insize to a cache line from the processor 1110, all the first to fourthsector data of a cache set may be updated. Alternatively, in the case ofreceiving the first data DATA1 equal in size to a sector from theprocessor 1110, only specific sector data of a plurality of sector dataof a cache set may be updated.

In operation S2150, the cache memory device 1120 may set at least onedirty bit corresponding to the first data DATA1 to the second logicalvalue indicating the dirty state. In an embodiment, in the case ofreceiving the first data DATA1 equal in size to a cache line from theprocessor 1110, all the first to fourth dirty bits D1 to D4 may be setto the second logical value. Alternatively, when the first address ADDR1indicates the third sector S3 and the first data DATA1 equal in size toa sector are received from the processor 1110, only the third dirty bitD3 may be set to the second logical value.

Because the processor 1110 transmits the write request of the write-backmanner, only data stored in the cache memory device 1120 may be updatedwithout an update of data stored in the memory device 1200. The datastored in the cache memory device 1120 may be different from the datastored in the memory device 1200, which correspond to the updated datain the cache memory device 1120.

FIG. 10C is a flowchart illustrating an operation of an electronicdevice of FIG. 1 , according to an embodiment. Referring to FIGS. 1, 2,and 4 , in operation S3010, the processor 1110 may transmit the writerequest of the write-through manner including the first address ADDR1and the first data DATA1 to the cache memory device 1120.

In operation S3020, in response to the write request, the cache memorydevice 1120 may determine whether data corresponding to the firstaddress ADDR1 are stored in the cache memory device 1120. The cachememory device 1120 may determine whether a cache hit or a cache missoccurs, based on the tag TAG. This is described with reference to FIG.10A in detail, and thus, additional description will be omitted to avoidredundancy. When it is determined that a cache hit occurs, the methodproceeds to operation S3140. When it is determined that a cache missoccurs, the method proceeds to operation S3030.

Operation S3030 to operation S3150 are identical to operation S2030 tooperation S2150 of FIG. 10B, and thus, additional description will beomitted to avoid redundancy. In operation S3160, the processor 1110 maytransmit the write request of the write-through manner including thesecond address ADDR2, the dirty information DI, and data to the memorycontroller 1130. The dirty information DI may include the first tofourth dirty bits DI1 to DI4 of a cache set corresponding to the secondaddress ADDR2. Because the processor 1110 transmits the write request ofthe write-through manner in operation S3010, both data stored in thecache memory device 1120 and data stored in the memory device 1200 maybe updated.

In operation S3170, based on the dirty information DI, the data, and awrite request including the second address ADDR2, the memory controller1130 may transmit the data mask signal DM to the memory device 1200together with the data from the processor 1110. In an embodiment, thememory controller 1130 may receive the write request including theaddress, the dirty information DI, and the data. The memory controller1130 may sequentially arrange the data to data bits corresponding to aburst length so as to be output to the first to sixteenth data lines DQ1to DQ16. The memory controller 1130 may generate the data mask signal DMbased on the dirty information DI. The memory controller 1130 may outputthe data and the data mask signal DM in synchronization with the datastrobe signal DQS. This is described above, and thus, additionaldescription will be omitted to avoid redundancy.

As described above, the electronic device 1000 according to the presentdisclosure may manage dirty information in units of sector smaller thana cache line. The electronic device 1000 may generate a data mask signalbased on dirty information managed in units of sector and may perform awrite operation on the memory device 1200 in units of sector.Accordingly, a sector of the cache memory device 1120, which is notupdated by the processor 1110, may not be stored in the memory device1200. According to the above description, unnecessary data storeoperations may be minimized, and thus, an error in the memory device1200 may decrease.

FIG. 11 is a block diagram illustrating a storage device according to anembodiment of the present disclosure. Referring to FIG. 11 , a storagedevice 2000 includes a memory controller 2100, a buffer memory 2200, anda nonvolatile memory device 2300. In an embodiment, the storage device2000 may be a high-capacity storage medium such as a solid state drive(SSD), a universal serial bus (USB) memory, a hard disk drive, or a USBstick.

The memory controller 2100 may exchange data in response to a requestfrom a host (not illustrated). In response to the request from the host,the memory controller 2100 may read data from the nonvolatile memorydevice 2300, may temporarily store the read data in the buffer memory2200, and may provide the read data to the host. Also, in response tothe request from the host, the memory controller 2100 may temporarilystore data “DATA” received from the host in the buffer memory 2200 andmay then program the data “DATA” in the nonvolatile memory device 2300.

To perform the above operation, the memory controller 2100 may providean address, a command, and a control signal to the nonvolatile memorydevice 2300 and may exchange data with the nonvolatile memory device2300. To perform the above operation, the memory controller 2100 mayprovide an address, a command, a control signal, and the data masksignal DM to the buffer memory 2200 and may exchange data with thebuffer memory 2200.

The memory controller 2100 may manage or control the nonvolatile memorydevice 2300. In an embodiment, the memory controller 2100 may performvarious maintenance operations, which are associated with thenonvolatile memory device 2300, such as mapping table management, badblock management, and wear leveling.

The buffer memory 2200 may operate under control of the memorycontroller 2100. For example, in response to signals received from thememory controller 2100, the buffer memory 2200 may store data or mayprovide the stored data to the memory controller 2100. In an embodiment,the buffer memory 2200 may be a dynamic random access memory (DRAM)device, but the present disclosure is not limited thereto.

The buffer memory 2200 may store a mapping table associated with thenonvolatile memory device 2300. In an embodiment, the buffer memory 2200may temporarily store data received from the host. Alternatively, thebuffer memory 2200 may temporarily store data read from the nonvolatilememory device 2300.

In response to signals received from the memory controller 2100, thenonvolatile memory device 2300 may output data or may program receiveddata. In an embodiment, the nonvolatile memory device 2300 may include aNAND flash memory. However, embodiments may not be limited thereto. Forexample, the nonvolatile memory device 2300 may include a volatilememory, such as a static RAM (SRAM), a DRAM, or a synchronous DRAM(SDRAM), or a nonvolatile memory, such as a read only memory (ROM), aprogrammable ROM (PROM), an electrically programmable ROM (EPROM), anelectrically erasable and programmable ROM (EEPROM), a flash memorydevice, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistiveRAM (RRAM), or a ferroelectric RAM (FRAM).

FIG. 12 is a block diagram illustrating a memory controller of FIG. 11 .Referring to FIGS. 11 and 12 , the memory controller 2100 may include aprocessor 2110, a cache memory device 2120, a read only memory (ROM)2130, a host interface circuit 2140, a buffer memory interface circuit2150, and a flash interface circuit 2160.

The processor 2110 may control overall operations of the memorycontroller 2100. The cache memory device 2120 may be a static randomaccess memory (SRAM) device. The ROM 2130 may store a variety ofinformation necessary for the memory controller 2100 to operate in theform of firmware.

In an embodiment, various information (e.g., a flash translation layerand a mapping table) necessary to control the nonvolatile memory device2300 may be stored to the cache memory device 2120 or the buffer memory2200 and may be managed or driven by the processor 2110.

The cache memory device 2120 may support an access speed higher than thebuffer memory 2200. As a portion of data stored in the buffer memory2200 is stored in the cache memory device 2120, a speed at which anaccess according to a request of the processor 2110 is made may beimproved. The cache memory device 2120 may include a plurality of cachesets. The cache memory device 2120 may manage a dirty bit in units ofsector, not in units of a cache line. In an embodiment, the cache memorydevice 2120 may include first to fourth dirty bits. A cache set isdescribed with reference to FIG. 4 in detail, and thus, additionaldescription will be omitted to avoid redundancy.

The memory controller 2100 may communicate with an external device(e.g., a host) through the host interface circuit 2140. In anembodiment, the host interface circuit 2140 may be based on at least oneof various interfaces such as a double data rate (DDR) interface, auniversal serial bus (USB) interface, a multimedia card (MMC) interface,a peripheral component interconnection (PCI) interface, a PCI-express(PCIe) interface, an advanced technology attachment (ATA) interface, aserial-ATA (SATA) interface, a parallel-ATA (PATA) interface, a smallcomputer small interface (SCSI) interface, an enhanced small diskinterface (ESDI), an integrated drive electronics (IDE) interface, amobile industry processor interface (MIPI), and a nonvolatilememory-express (NVMe) interface.

The memory controller 2100 may communicate with the buffer memory 2200through the buffer memory interface circuit 2150. In an embodiment, thememory controller 2100 may provide various signals to the buffer memory2200 through the buffer memory interface circuit 2150. In an embodiment,the buffer memory interface circuit 2150 may include a DRAM interfacesuch as a double data rate (DDR) interface, a low-power DDR (LPDDR)interface, or a universal serial bus (USB) interface.

The buffer memory interface circuit 2150 may include a data mask controlcircuit 2151 which operates similarly as discussed with reference toFIGS. 4 through 11 . The data mask control circuit 2151 may receive thedirty information DI from the cache memory device 2120. The data maskcontrol circuit 2151 may output a data mask signal DM through a datamask line based on the received dirty information DI so that the buffermemory interface circuit 2150 performs a flush operation using a maskwrite operation.

The memory controller 2100 may communicate with the nonvolatile memorydevice 2300 through the flash interface circuit 2160. In an embodiment,the memory controller 2100 may provide various signals (e.g., CLE, ALE,RE/, WE/, CMD, ADDR, SQRI, and DT) to the nonvolatile memory device 2300based on the flash interface circuit 2160. In an embodiment, the flashinterface circuit 2160 may include a NAND interface such as a toggleNAND interface or an open NAND flash interface (ONFI).

The memory controller 2100 illustrated in FIG. 12 is, and the presentdisclosure is not limited thereto. The memory controller 2100 mayfurther include various components such as an error correction code(ECC) engine and a randomizer.

As described with reference to FIGS. 1 to 10C, the storage device 2000according to an embodiment of the present disclosure may manage dirtyinformation in units of sector smaller in size than a cache line. Thestorage device 2000 may output the data mask signal DM to the buffermemory 2200 through the data mask line based on the dirty information.The buffer memory 2200 does not store sector data of the cache memorydevice 2120, which are not updated, based on the data mask signal DM.

FIG. 13 is a block diagram illustrating an SSD system 3000 according toan embodiment of the present disclosure. Referring to FIG. 13 , the SSDsystem 3000 includes a host 3100 and an SSD 3200.

The SSD 3200 exchanges signals SIG with the host 3100 through a signalconnector 3201 and is supplied with a power PWR through a powerconnector 3202. The SSD 3200 includes an SSD controller 3210, aplurality of flash memories 3221 to 322 n, an auxiliary power supply3230, and a buffer memory 3240. In an embodiment, the SSD controller3210 may manage dirty information in units of sector and may generate adata mask signal based on the dirty information, which is described withreference to FIGS. 1 to 12 . Accordingly, a sector of a cache memorydevice, which is not updated, may not be stored in the buffer memory2200. According to the above description, unnecessary data storeoperations may be minimized, and thus, an error in the buffer memory3240 may decrease.

The SSD controller 3210 may control the plurality of flash memories 3221to 322 n in response to the signals SIG received from the host 3100. Theplurality of flash memories 3221 to 322 n may operate under control ofthe SSD controller 3210. The auxiliary power supply 3230 is connectedwith the host 3100 through the power connector 3202. The auxiliary powersupply 3230 may be charged by the power PWR supplied from the host 3100.When the power PWR is not smoothly supplied from the host 3100, theauxiliary power supply 3230 may power the SSD 3200.

According to the present disclosure, as dirty information is stored in acache memory device in units of sector smaller in size than a cache lineand the dirty information is provided to a memory controller, the memorycontroller may generate a data mask signal. A memory device mayselectively store data based on the data mask signal received from thememory controller. As such, data of the cache memory device, which arenot updated, may be prevented from being stored in the memory device.Accordingly, an electronic device having improved stability and capableof minimizing power consumption, a system-on-chip, and an operatingmethod thereof are provided.

While the present disclosure has been described with reference toembodiments thereof, it will be apparent to those of ordinary skill inthe art that various changes and modifications may be made theretowithout departing from the spirit and scope of the present disclosure asset forth in the following claims.

What is claimed is:
 1. An electronic device comprising: a cache memoryincluding a memory space configured to store a first cache set includinga plurality of sector data and a plurality of dirty bits, each of theplurality of dirty bits representing whether corresponding sector dataof the plurality of sector data are modified; a memory controllerconnected to a plurality of data lines and a data mask line, andconfigured to: receive the plurality of sector data and the plurality ofdirty bits from the cache memory, set a logic level of a data masksignal based on a logic level of each of the plurality of dirty bits,and output the plurality of sector data through the plurality of datalines and the data mask signal through the data mask line; and a memorydevice connected to the plurality of data lines and the data mask line,and configured to: receive the plurality of sector data through theplurality of data lines, and receive the data mask signal through thedata mask line, wherein the memory controller is further configured totransmit a first mask write (MWR) command to the memory device through aplurality of command/address (CA) lines, wherein the memory device,after receiving the first MWR command, receives the plurality of sectordata and the data mask signal, wherein the memory controller isconfigured to: activate, based on a logic value of a first operationcode, a data mask function of the memory device, the logic value of thefirst operation code being stored in a first mode register of the memorydevice, wherein the memory controller transmit the first MWR command tothe memory device in which the data mask function has been activate; anddeactivate, based on a logic value of a second operation code, a databus inversion function of the memory device, the logic value of thesecond operation code being stored in a second mode register of thememory device, and wherein the mask data line is a data inversion lineof the memory device in which the data bus inversion function has beendeactivated.
 2. The electronic device of claim 1, wherein the memorycontroller is configured to write first sector data of the plurality ofsector data stored in the cache memory to the memory device during afirst time period and write second sector data of the plurality ofsector data stored in the cache memory during a second time periodsubsequent to the first time period, wherein the memory controller isconfigured to issue the data mask signal to the memory device, andwherein the memory controller is configured to: set, based on a logiclevel of a first dirty bit associated with the first sector data, alogic level of the data mask signal to be applied during the first timeperiod; and set, based on a second dirty bit associated with the secondsector data, a logic level of the data mask signal to be applied duringthe second time period.
 3. The electronic device of claim 2, wherein inresponse to the logic level of the first dirty bit indicating that thefirst sector data are not modified, the memory controller deactivatesthe data mask signal during the first time period so that the memorydevice, in response to the first MWR command and the deactivated datamask signal, blocks the first sector data from being stored in thememory device, and wherein in response to the logic level of the seconddirty bit indicating that the second sector data are modified, thememory controller activates the data mask signal during the second timeperiod so that the memory device, in response to the first MWR commandand the activated data mask signal, stores the second sector datareceived from the memory controller.
 4. The electronic device of claim1, wherein a size of each of the plurality of sector data is smallerthan a size of a cache line, and wherein the size of the cache line is aminimum access unit of data to be transmitted to the memory device inresponse to a write request of the memory controller.
 5. An operatingmethod of an electronic device which includes a cache memory including amemory space configured to store a first cache set including a pluralityof sector data and a plurality of dirty bits, each of the plurality ofdirty bits representing whether corresponding sector data of theplurality of sector data stored in the cache memory are modified, amemory device, and a memory controller between the cache memory and thememory device, the method comprising: setting, by the memory controller,a logic level of a data mask signal based on a logic level of each ofthe plurality of dirty bits; issuing, by the memory controller, a firstmask write (MWR) command to the memory device through command/address(CA) lines connected thereto; transmitting, by the memory controller,the plurality of sector data stored in the cache memory to the memorydevice through a plurality of data lines connected thereto, and a datamask signal to the memory device through a data mask line connectedthereto; receiving, by the memory device, the plurality of sector dataand data mask signal after receiving the first MWR command; activating,by the memory controller, based on a logic value of a first operationcode, a data mask function of the memory device, the logic value of thefirst operation code being stored in a first mode register of the memorydevice; and deactivating, by the memory controller, based on a logicvalue of a second operation code, a data bus inversion function of thememory device, the logic value of the second operation code being storedin a second mode register of the memory device, wherein the first MWRcommand is transmitted to the memory device in which the data maskfunction has been activated and the data bus inversion function has beendeactivated.
 6. The method of claim 5, wherein the transmitting of theplurality of sector data and the data mask signal includes: outputting,by the memory controller, first sector data of the plurality of sectordata stored in the cache memory through the plurality of data linesduring a first time period; and outputting, by the memory controller,second sector data of the plurality of sector data stored in the cachememory through the plurality of data lines during a second time period,and wherein the setting of the logic level of the data mask signalincludes: setting, based on a logic level of a first dirty bitassociated with the first sector data, a logic level of the data masksignal to be applied during the first time period; and setting, based ona logic level of a second dirty bit associated with the second sectordata, a logic level of the data mask signal to be applied during thesecond time period.
 7. The method of claim 5, wherein the transmittingof the plurality of sector data and the data mask signal includes:outputting, by the memory controller, after a given time elapses from atime when the first MWR command is issued, the plurality of sector datato the memory device through the plurality of data lines connectedthereto.
 8. The method of claim 5, wherein a size of each of theplurality of sector data is smaller than a size of a cache line, andwherein the cache line is a minimum access unit of data to betransmitted to the memory device in response to a write request of thememory controller.
 9. A solid state drive (SSD) controller comprising: acache memory including a memory storage configured to store a firstcache set including first sector data and second sector data, and afirst dirty bit and a second dirty bit which are associated with thefirst sector data and the second sector data, respectively; and a buffermemory interface circuit configured to flush, based on a logic level ofeach of the first and second dirty bits, the first and second sectordata to an external memory device, wherein, when the first dirty bitindicates a dirty state and the second dirty bit indicates a cleanstate, the buffer memory interface circuit masks the first sector datato generate first masked sector data, outputs the first masked sectordata to the external memory device through a plurality of data linesduring a first time period, and outputs the second sector data to theexternal memory device through the plurality of data lines during asecond time period after the first time period, and wherein the buffermemory interface circuit is configured to: activate, based on a firstoperation code stored in a first mode register of the external memorydevice, a data mask function; and deactivate, based on a secondoperation code stored in a second mode register of the external memorydevice, a data bus inversion function.
 10. The solid state drivecontroller of claim 9, wherein the buffer memory interface circuit isconfigured to transmit, before outputting the first and second sectordata to the external memory device through a plurality of data linesconnected thereto, a first mask write (MWR) command to the externalmemory device through command/address (CA) lines connected thereto. 11.The solid state drive controller of claim 9, wherein the buffer memoryinterface circuit is further configured to deactivate a mask signal tobe output through a data mask line during the first and second timeperiods.
 12. The solid state drive controller of claim 9, wherein a sizeof each of the first and second sector data is smaller than a size of acache line, and wherein the size of the cache line is a minimum accessunit of data to be transmitted to the external memory device in responseto a write request of the buffer memory interface circuit.
 13. A memorydevice comprising: a memory cell array including a plurality of memorycells; an input/output circuit configured to receive a plurality ofsector data through a plurality of data lines; and a control logiccircuit configured to: receive a first mask write (MWR) command throughcommand/address (CA) lines; receive a data mask signal through a datamask line; selectively store the plurality of sector data in the memorycell array in response to the data mask signal, wherein the data masksignal is generated from an external memory controller based on aplurality of dirty bits associated with the plurality of sector data,respectively, and wherein, after receiving the first MWR command, theinput/output circuit receives the plurality of sector data and thecontrol logic circuit receives the data mask signal; block, in responseto a logic high level of the data mask signal, first sector data amongthe plurality of sector data from being stored in the memory cell array,the first sector data being received during a time when the data masksignal is at the logic high level; and store, in response to a logic lowlevel of the data mask signal, second sector data among the plurality ofsector data in the memory cell array, the second sector data beingreceived during a time when the data mask signal is at the logic lowlevel.
 14. The memory device of claim 13, further comprising: aplurality of mode registers including a second mode register and a firstmode register, wherein the control logic circuit is configured to:activate, based on a first operation code stored in the first moderegister, a data mask function; and deactivate, based on a secondoperation code stored in the second mode register, a data bus inversionfunction.
 15. The memory device of claim 13, wherein, after a given timeelapses from a time when the first MWR command is received, theinput/output circuit receives the plurality of sector data through theplurality of data lines.